The present invention relates to a polishing compound to be used for chemical mechanical polishing in a process for production of semiconductor integrated circuits and further relates to a polishing method for a metal layer and/or a barrier layer formed on a semiconductor substrate, employing such a polishing compound.
At present, in order to meet the demands for further microsizing, higher performances, higher speed and lower power consumption of various digital household equipments, mobile computers, portable information/communication devices, etc., studies for microsizing and high densification are continued also with respect to semiconductor integrated circuits (hereinafter referred to simply as semiconductor apparatus or semiconductor devices) to be used as incorporated as key components of such instruments. For this purpose, a highly densified multilayer interconnection structure is being seeked wherein a wiring pattern with a fine line width of submicron design rule is embedded on an insulating layer formed on a substrate, and such fine wiring structures are multi-layered with an insulating layer interposed.
As microsizing and high densification of semiconductor devices advance by such multilayer interconnection structures, irregularities of the surface of each layer will increase, and steps of such irregularities tend to exceed the focal depth of a lithography optical system. Such irregularities bring about various problems such that they will cause disconnection or short circuit in the multilayer interconnection process. Accordingly, it is essential to carry out planarization of the semiconductor substrate surface at an appropriate stage of the production process.
Accordingly, as an important key technology for planarization treatment, attention has been drawn to chemical mechanical polishing (hereinafter sometimes referred to as CMP), which is a polishing technique whereby an insulating film and/or a metal film formed on each layer (on the semiconductor substrate) can be ultraprecisely flattened.
Heretofore, as a wiring material for a semiconductor, a wiring material of aluminum (Al) type is used in many cases, since patterning can be carried out easily by e.g. dry etching. However, in the case of Al type, under a design rule for a wiring line width of at most 0.25 xcexcm, insulation resistance between elements tends to be not negligible, whereby a substantial wiring delay time will result. In addition, there is a problem such that a power loss due to charge and discharge caused by parastic capacity among Al type wirings, will be a serious hindrance against reduction of power consumption of mobile instruments, etc.
Therefore, there has been an attempt to use copper (Cu) wiring and Cu alloy wiring (hereinafter sometimes referred to simply as Cu or the like) which are materials having lower resistance, as the material for multilayer interconnection for semiconductor devices of future generation. With Cu or the like, the dry etching temperature is required to be higher, and patterning of a thin film by dry etching can not so easily be carried out as in the case of Al. Therefore, usually, Cu or the like is embedded in wiring grooves and/or via holes (contact grooves) on interlaminar insulating layers by e.g. electrolytic plating, followed by CMP polishing for planarization to remove excess Cu or the like. This is a technique so-called Damascine method proposed by IBM, and thus, the CMP technique for metal such as Cu (so-called metal CMP) will be the main technique for semiconductor devices in future.
A general principle of metal CMP is considered to be as follows. Namely, an oxidizing agent in the polishing compound oxidizes the metal surface to form a thin film of a metal oxide on the surface. This metal oxide is usually in a passive state, and on the passivated surface, no further reaction proceeds. The thin film of such a metal oxide is usually brittle than the thin film of the metal itself, and thus, the portion in contact with the polishing pad can easily be mechanically removed by polishing abrasive grains, whereby the metal surface will again be exposed. It is explained that such an exposed surface is again oxidized, and such a process is repeated, whereby polishing of the metal film becomes possible.
However, according to a study carried out by the present inventors, among metals, in the case of Cu or the like, it is not so easy to apply CMP as compared with e.g. tungsten. One of the reasons is that the mechanism for forming the thin film of copper oxide is not clearly understood. To apply CMP, it is basically necessary to form a coating film of copper oxide on the surface of metallic copper. However, by a conventional polishing compound, it has been often difficult to form a coating film of copper oxide having a proper thickness or the minimum thickness required. If a thin film of copper oxide is formed in a thickness more than necessary, such a thick copper oxide film will not be so brittle, can not easily be removed by polishing abrasive grains, but will rather hinder such polishing, whereby there will be a problem that the polishing rate substantially decreases.
Thus, it is required to provide a polishing compound suitable for microsizing of semiconductor devices, which used to be difficult by a conventional polishing compound, particularly a polishing compound which is capable of polishing a metal layer of Cu or the like at a sufficient polishing rate and which is excellent in global planarization of the surface of a semiconductor substrate.
The object of the present invention is to provide a polishing compound having an adequate polishing rate for metal CMP in the process for production of a semiconductor device, particularly to provide a polishing compound capable of accomplishing an adequate polishing rate at the time of polishing a metal layer of Cu or the like.
(1) The present invention provides a polishing compound for polishing a metal layer and/or a barrier layer formed on a semiconductor substrate, which is a polishing compound for chemical mechanical polishing in a process for production of a semiconductor device and which comprises polishing abrasive grains and a peptide.
(2) Further, the present invention provides a method for polishing a semiconductor substrate, characterized in that with the above polishing compound supported on a polishing cloth of a chemical mechanical polishing apparatus, i.e. specifically, while supplying a slurry of the above polishing compound to an abrasive cloth of a chemical mechanical polishing apparatus, at least a part of a metal layer and/or a barrier layer of a semiconductor substrate is polished.